Imec, GlobalFoundries and Samsung are presenting at IEDM 2012 the results of simulations on 14nm finFET structures that used strained, or relaxed, silicon or germanium channels on the basis that this offers lower risk than moving to III/V materials.
They found that it was hard to beat strained silicon for p-channel transistors: the impressive amounts of strain applied so far have reduced the traditional gap between n- and p-channel transistors for a couple of generations now. However, by laying a germanium layer over a silicon germanium strain-relaxed buffer, they predicted almost a 50 per cent improvement over strained silicon.
For n-channel transistors, a combination of silicon germanium and carbon-doped silicon layers boosted doubled performance over more conventional strained silicon. A move to germanium with relaxed channels saw an increase of 120 per cent over strained silicon, largely due to a six-fold increase in mobility along the fin sidewalls. A further silicon germanium stressor extended the increase to 210 per cent.
The team used nano-beam diffraction to check that the stressed layers came out with the expected amounts of strain.
There are still issues with using germanium channels, although some of the materials science for making gates has been developed for more exotic planar CMOS processes. Freescale demonstrated a technique for MOS gate fabrication in 2005 that was applied to RF power transistors. At this year’s IEDM, TSMC describes a process that overcomes some of the problems of growing germanium fins directly on silicon in such a way that troublesome crystal dislocations are contained.
Circuit modelling for tunnel FETs
Two other papers focused on a potential device architecture for the future: the tunnel FET. One issue that faces designers is the lack of circuit models that accurately present a device types that operates somewhat differently to today’s CMOS transistors.
A pair of researchers from the Hong Kong University of Science and Technology has developed surface potential-based models that provide the current-voltage and charge-voltage descriptions that can be used in a circuit simulator. Verifying the results using TCAD, the group has simulated circuits based on TFETs that include inverters, ring oscillators, NAND gates and SRAMs.
Another issue for the TFET revolves around materials choice. Indium arsenide has a very small band-gap, so is a prime contender for a future TFET material. But it has the tendency to form interface states that disrupt the device’s behavior.
The bad news, a team from DIEGM-IUNET in Udine, Italy and IMEP-LAHC in Grenoble, France found in their quantum-transport simulations, is that a single interface trap can degrade the subthreshold slope of what should be a device with a much better slope than that found in CMOS transistors and the overall impact of traps is worse than in CMOS transistors. A further issue, the researchers found, is that the traps increase the temperature dependence of IV curves, largely due to phonon-assisted tunnelling.
Applying Spice to MEMS
At the other end of the geometry scale, a team from the University of Tokyo, NTT and the Tokyo Institute of Technology has updated its work on using Spice to perform multi-physics simulations of integrated MEMS devices. Members of the team presented the technique a couple of years ago at the SSDM conference. In their most recent work, the researchers have extended the simulation capability of the models and tested them on a device that inciudes digital torsion mirrors.
Spice-like techniques have been used for some time in MEMS design. The Sugar simulator, which was named in honor of Spice because of the way its designed and distributed, uses the same basic architecture of differential-equation solvers to run its MEMS models. Sugar runs within the Matlab environment whereas the University of Tokyo system uses the Spice simulator itself. In this particular case the simulator is Linear Technology’s LTSpice.
The Tokyo simulator works largely by reinterpreting mechanical equations as behavioral current sources. To calibrate the model, the team tested against an eight-channel torsion mirror device fabricated on Toshiba’s DMOS4 process with a thick SOI layer used for the MEMS sections. “Thanks to the nature of compact models, it took only a minute on a notebook PC to simulate the behavior with more than 10,000 sampling points,” they report.