GlobalFoundries and Samsung talk finFET progress at CPTF

By Chris Edwards |  1 Comment  |  Posted: February 5, 2013
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations: , ,

At the Common Platform Technology Platform, foundries in the alliance used the Technology Forum in California this week to talk about the progress they have made to get finFETs into production but also preparing to extend the life of the existing 28nm processes, as GlobalFoundries gears up to release the process design kit for an FD-SOI version.

Mike Noonen, executive vice president of global sales and marketing at GlobalFoundries, described how the company used a design based on a dual Cortex A9 processor to benchmark the process that the company intends to introduce for the 14nm node. Using ARM’s Artisan libraries, Noonen said compared to the existing 28nm process, the 14nm technology could deliver a 62 per cent reduction in power for the same performance. This was possible using a nine-track standard-cell library on the finFET-based process versus a 12-track library for the bulk. Alternatively, a 61 per cent improvement in performance is possible for a given power level.

“It shows what can be done with the finFET platform,” said Noonen. “What we have built with Common Platform is a very SoC-friendly solution where you can dial in your required levels of performance.”

Using the company’s experience of going with a gate-first high-k, metal-gate process in an environment where other companies had gone with gate-last, Samsung Electronics executive vice president KH Kim claimed the Common Platform’s approach to finFETs would be successful.

“When we approached customers with gate-first, they said it was risky. But it turned out that gate-first was really successful. Our Common Platform collaboration has been really successful and it will be successful in the future,” Kim argued.

Kim said work with other foundries and EDA companies such as Cadence Design Systems, Mentor Graphics and Synopsys on design, modelling and extraction had guided the development of the 14nm finFET process. Kim said device uniformity at the manufacturing level is vital to keeping process variation under control. Other issues have raised their heads. One – parasitic resistance – has become a major issue at 14nm which has meant work on middle-of-line layout and routing schemes together with techniques such as Schottky barrier height modulation.

“By collaborating with partners we are ready to offer this technology to our customers. There are challenges to overcome…but you can rely on us,” Kim claimed, adding that a number of multiproject wafer runs are being scheduled this year for the 14nm finFET process.

Although Samsung is working to bring the 14nm technology into production, 28nm remains a key part of the offering, Kim said. “We believe 28nm will be a very long-lived node and Samsung can offer a proven HKMG technology.”

GlobalFoundries is readying a further variant of its 28nm process through the deal it signed with STMicroelectronics last year. This will provide customers with the option of mixing and matching silicon-on-insulator circuitry with bulk CMOS. “We are leveraging the front end of line of the 28nm SLP platform,” said Noonen. “The back-end of the process is pretty much identical to the 28SLP platform. The ingenuity of this is to have this very think silicon channel over an insulator to offer dielectric isolation. You can really dial in optimum performance and have a speed boost through back-biasing. It is a simpler process that offsets the cost of the substrate and it offers significant reuse of IP from bulk processes.”

Noonen added: “The PDK for this technology is available this quarter.”

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