SNUG 2016: Aart de Geus looks beyond the linear design flow
Do the synapses in the human brain offer a new model for the design flow in a Smart Everything world?
EDA
SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
Cadence moves into safer design with Virtuoso changes
Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
HyperLynx made broader and easier to use
HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
Meet the Electronic System Design Alliance
The EDA Consortium is rebranding and extending its activities to better reflect all the tools and services that now comprise IC design.
Synopsys updates custom design tools for the finFET age
Synopsys is updating its custom design tools to make working with finFET based processes easier.
MEMS contest launches at DATE
The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
IP implementation variety drives latest partnerships
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
Mentor builds out verification IP for memory
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
Six quick videos introduce key formal verification concepts
Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.