The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
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