A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
View All Sponsors