March 13, 2022
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
May 21, 2019
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
August 30, 2016
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
April 4, 2016
HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
January 14, 2016
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
May 24, 2015
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
April 28, 2015
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
May 17, 2014
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.