EDA

The functional verification specialist will discuss the latest updates to Ascent and Meridian - and offer top quality espresso at this year's conference.

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.

A new dedicated automotive power tester helps cut simulation errors to just 0.5% with more faithful calibration.

Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.

Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.

The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.

Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.