Cadence Design Systems

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.

An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.

Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.

Conference addresses formal verification techniques at levels to suit beginners through to experts

New version of Vivado adds verification features and speed, extends Zynq support

Cabling and its weight are helping to drive integration and a shift towards wireless communication within cars, says NXP's automotive CTO.