Cadence Design Systems

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.

Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.

ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.

The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.

Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.

Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.