March 16, 2016
The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
February 2, 2016
Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
December 18, 2015
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
December 7, 2015
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
November 16, 2015
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
November 12, 2015
But the bridge standard's European backers still need greater support from the big EDA vendors.
October 9, 2015
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
October 6, 2015
Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
July 15, 2015
The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
June 18, 2015
Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.