Cadence Design Systems

May 18, 2015

Vehicle ethernet adds to IP virtual reference kits for board design

Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , ,   |  Organizations:
May 11, 2015

Formal verification conference offers ARM, Broadcom, Imagination insights, online access

Conference addresses formal verification techniques at levels to suit beginners through to experts
May 5, 2015

Xilinx updates Vivado with CDC, faster verification, third-party flows, and lab edition

New version of Vivado adds verification features and speed, extends Zynq support
Article  |  Topics: Product  |  Tags: ,   |  Organizations: , , , ,
April 29, 2015

Automotive integration led by cabling concerns, says NXP

Cabling and its weight are helping to drive integration and a shift towards wireless communication within cars, says NXP's automotive CTO.
April 28, 2015

Cadence upgrades debug for system-level era

Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
April 22, 2015

Fusion core targets voice-activated devices

Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
April 21, 2015

Cadence updates OrCAD line with additions for PCB manufacturability and integrity

Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
March 18, 2015

ARM and Cadence agree to share IP access

ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations: ,
March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:

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