Xilinx has updated the Vivado Design Suite for its FPGAs and SoCs.The 2015.1 release includes faster simulation, a free Lab Edition with a subset of the overall functionality, third-party simulation flows, interactive clock domain crossing (CDC) analysis, and advanced system performance analysis with the Xilinx Software Development Kit (SDK).
Vivado Lab Edition is a free programming and debug edition of the Vivado Design Suite, for use in labs which don’t need the features of the full tool suite. It includes the Vivado Device Programmer, Vivado Logic and Serial I/O Analyzer, and memory-debug tools.
Xilinx says the 2015.1 release of Vivado Design Suite can halve LogiCORE IP compile times, boosting overall simulation performance by 20 per cent.
The release includes simulation flows with Alliance Program members including Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.
The 2015.1 release also adds interactive CDC analysis, which should enable CDC issues to be recognised and debugged earlier in the design flow.
To accelerate the development of the Zynq-7000 All Programmable SoC, Xilinx has extended its system performance and analysis toolbox so that embedded software developers can analyze the performance and bandwidth of their SoC design, to cover key performance metrics for the processor subsystem, as well as bandwidth analysis between that subsystem, the programmable logic and external memories.
System modeling designs using AXI traffic generators are provided for the Zynq-7000 All Programmable SoC ZC702 and ZC706 evaluation boards.
The Vivado Design Suite 2015.1 is available now with support for Xilinx’s 7 series FPGAs and SoCs and UltraScale devices.