ULP

June 10, 2015

TSMC adds Cadence and Imagination subsystems for IoT

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.

Article | Topics: Commentary, Digital/analog implementation, Blog - EDA, Embedded, IP | Tags: 28nm, 40nm, 55nm, DAC 2015, DSP, internet of things, MCU, MIPS, peripheral, PowerVR, subsystem, Tensilica, ULP | Organizations: Arm, Brite Semiconductor, Cadence Design Systems, Imagination Technologes, SMIC, TSMC

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