Cadence Design Systems

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.

German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.

Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.

Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.

ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.

The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.

Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.