May 11, 2017
Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.
May 1, 2017
Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
April 12, 2017
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
March 24, 2017
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
March 7, 2017
An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
February 27, 2017
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
February 15, 2017
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
November 15, 2016
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
October 26, 2016
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
October 10, 2016
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.