Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
Cadence Design Systems
The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.
RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
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