Cadence Design Systems

October 6, 2015

Tensilica vision processor cuts power through memory changes

Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
July 15, 2015

PSpice builds interfaces to PCB and system-level cosimulation

The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
June 18, 2015

The road to 7nm sees patterning multiply

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
June 16, 2015

Collaboration let HiSilicon accelerate 16nm finFET plans

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
June 10, 2015

SoC verification ‘should use software more’

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
June 10, 2015

TSMC adds Cadence and Imagination subsystems for IoT

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
June 8, 2015

Formal integration enhances bug-hunting for Cadence

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
June 5, 2015

DAC 2015: Cadence Design Systems at the Design Automation Conference

An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.
Article  |  Topics: Conferences, Blog - EDA, Embedded, - General, Blog - IP, PCB  |  Tags:   |  Organizations:
June 3, 2015

Cadence deploys parallel strategy for faster synthesis

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
May 24, 2015

Cadence updates Allegro with PCB production and routing tools

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:

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