Cadence Design Systems

Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.

Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.

Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.

ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (February 20)

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.