Cadence Design Systems

April 22, 2015

Fusion core targets voice-activated devices

Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
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April 21, 2015

Cadence updates OrCAD line with additions for PCB manufacturability and integrity

Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.
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March 18, 2015

ARM and Cadence agree to share IP access

ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.
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March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
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February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
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February 16, 2015

CDNLive Silicon Valley: last chance for early bird discount

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (February 20)
Article  |  Topics: Conferences, Blog - EDA, Embedded, IP, PCB  |  Tags: ,   |  Organizations: ,
January 28, 2015

Cadence updates Sigrity tools and license options

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.
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January 14, 2015

Cadence updates Xtensa with memory and power saving features

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
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January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
December 11, 2014

Use-cases drive high-level verification tool

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.

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