DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
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