Cadence Design Systems has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
In the 16.6 is the Allegro PCB Designer Manufacturing Option, designed to speed up the creation of release-to-manufacturing packages for products. It includes the Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules. Cadence claimed the Documentation Editor module can speed up overall fabrication documentation by up to 60 percent.
The Allegro Rules Developer and Checker lets users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and tuned for an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks within a PCB environment.
SGI uses manufacturing option
“We use Cadence software for designing printed circuit boards from concept to production for our SGI ICE X and SGI UV platforms. The technology in the Allegro PCB Manufacturing Option has enabled us to reduce the amount of time spent creating and maintaining PCB documentation by as much as 60 percent,” said Cassio Conceicao, executive vice president and chief operating officer of SGI. “The result is shorter design cycle times, lower costs and a smoother handoff to manufacturing.”
For PCB layout work, the 16.6 release adds a number of automated assists for laying out high-speed signal traces. They include the insertion of return path vias while routing differential pairs to provide a ground current return path. Another update avoids the coupling of high-speed signals to the FR-4 fabric weave, making it easy for designers to create off-angle routes based on user-defined parameters.
There are also facilities to adjust the spacing for signals used by interfaces such as DDR3 and DDR4, allowing users to compress signals in high-density route areas, and to spread signals to avoid crosstalk between signals or make space for tuning the signal paths.
A new shape-editing AppMode lets users create and modify complex shape geometries more easily for copper shapes, flex cover lay geometries and complex pad shapes.