TSMC adds Cadence and Imagination subsystems for IoT

By Paul Dempsey |  No Comments  |  Posted: June 10, 2015
Topics/Categories: Commentary, Digital/analog implementation, Blog - EDA, Embedded, IP  |  Tags: , , , , , , , , , , , ,  | Organizations: , , , , ,

We’re going to see quite a lot of these over the next few months. TSMC, the world’s largest foundry, has continued to build out its offering for the Internet of Things (IoT) with the announcement of two more subsystem packages based on its 55nm ultra-low-power (ULP) process.

The latest agreements are with Cadence Design Systems and Imagination Technologies.

The Cadence subsystem will integrate the company’s Tensilica Fusion DSP alongside its other IP in analog, peripheral and sensor interfaces. Users will be able to select an additional applications processor, if needed.

The Imagination agreement covers a wide range of subsystems, with entry-level options based on the MIPS M-class CPU while more advanced options leverage the PowerVR core, higher end MIPS CPUs, Ensigma RPUs and RF.

They follow on from the joint TSMC-ARM announcement last week for a 55nm subsystem based on the Cortex-M.

Subsystem customers

Explicit in all the TSMC deals – as well as the Brite Semiconductor-SMIC-CEVA subsystem also just announced – is a need to draw upon various IP blocks available from the partner to create near turnkey reference designs and meet the demands of an emerging type of customer.

Suk Lee, senior director in TSMC’s Design Infrastructure Marketing Division, said, “In order to simplify our customers’ designs and shorten their time-to-market, TSMC and our ecosystem partners are transitioning from chip-design enablers to subsystem enablers.” (our italics)

Growth due to the IoT is largely driven by companies with limited electronics engineering expertise. Many are traditional industrial players looking to create ‘smarter’ products, and there is also a raft of tiny start-ups with highly focused goals.

The 55nm node is emerging as the preferred process for IoT platforms although an interesting aspect of the TSMC-Cadence deal does envisage further scaling to the foundry’s 40ULP and 28ULP offerings “as additional performance is needed for more compute intensive applications in the future”.






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