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June 8, 2015

Formal integration enhances bug-hunting for Cadence

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
September 3, 2014

DVCon Europe focuses on systems design and verification

Focus on systemic issues matches DVCon Europe event to European interests
Article  |  Topics: Conferences, Verification  |  Tags: , , , ,   |  Organizations:
November 19, 2012

‘Process and metrics before tools for better verification’

Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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