Cadence Design Systems has expanded its formal verification tools into RTL signoff with the addition of two apps to JasperGold that handle clock-domain crossing and linting.
Pete Hardee, director of product management for JasperGold at Cadence, said: “The checks that people used to do later in the flow – at the netlist stage – are moving forward in the flow. We are catching more of the bugs earlier on so there is less code churn later on.”
Tom Beckley, general manager of R&D in the custom IC and PCB division at Cadence, said in his keynote at CDNLive EMEA, organizations want to maximize IP reuse across different implementations. “We want to make sure RTL is high quality and you can make it portable and robust. You don’t want to get to the netlist stage and find you have an issue.”
The superlint app handles a variety of RTL checks that support design for test, to answer questions such as “do I have observability?” Hardee said. The checks include X assignment, arithmetic overflow, reachability, livelock, deadlock, and bus contention.
“There are structural checks that a lot of the tools today are handling. But there are other checks that need formal intelligence that does more than a traditional structural check,” Hardee said.
Hardee said the company has worked on waiver management. “Violation noise is the biggest customer complaint we hear about the existing tools.”
The main aim is to cut the number of situations where a waiver is issued for a particular case but later checks continue to flag up errors. The app will honor waivers but they can be made conditional. Hardee gave as a example a check for situations such as whether a quasi-static signal will be held static. “If that check fails we put it back in as a violation,” he said.