Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
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