May 16, 2017
Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
February 25, 2015
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
June 2, 2014
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
May 24, 2014
More lint rules, better SystemVerilog support, links to MATLAB and Simulink