Cadence tunes up simulators and FPGA prototyping

By Chris Edwards |  No Comments  |  Posted: February 27, 2017
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , ,  | Organizations: ,

Cadence Design Systems has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.

The changes to the simulators come as the result of the 2016 acquisition and integration of Israel-based Rocketick Technologies. The company developed a method for analyzing, decomposing and partitioning the hardware descriptions used in event-driven simulation across multiple processor cores. Cadence’s focus in the short term has been to work on performance for DFT and gate-level simulation to reduce the bottlenecking that now occurs towards the end of a project. But Adam Sherer, group director of marketing at Cadence, claimed the changes made mark the next step in the evolution of simulation, which moved from interpreted to compiled code more than a decade ago.

“Rocketick had a production-proven technology for multicore and a scalable one. We believe this is creating a third generation of simulator,” said Sherer.

Simulation refactored

Rather than continue with a separate line of simulators Sherer said the company refactored its Incisive software for the addition of the Xcelium parallel simulator. “We architected parts of the simulator to make it ready for multicore and better connect it with the Rocketick engine.”

The re-architecting and a new randomization engine has helped single-core throughput as well. “We see an average 2x speed-up on single core where we are running hundreds of jobs in regression.”

Sherer said the approach used by the compilation engine to separate loosely connected parts of the design from each other not only allows parallel simulation but improved handling of complex event-driven scenarios such as those encountered in DFT simulation where the primary aim of the test vectors is to stimulate as much of the logic in parallel as possible.

“Multicore simulation can reduce the event-dependency effect. You don’t feel the impact of the multiple events as much because you can distribute them among the multiple cores,” Sherer said. Further work to analyze the test vectors themselves may yield further improvements in the future.

Sherer said the ability to spread events among processor cores will also help with the use of portable stimulus, where SoC-level scenarios are assembled from multiple unit-level tests.

Protium bring-up speed-up

Although the company has upgraded the FPGAs in its Protium hardware prototyping system to Xilinx’ Ultrascale devices, the bigger changes are on the software side. The company has aligned the compile flow of Protium with that of the Palladium line of emulators so that they can share the same RTL descriptions. This reduces the bring-up time for FPGA prototyping down to a matter of days, according to Frank Schirrmeister, senior group director of product management and marketing at Cadence. That will help get software engineers writing code for the target SoC more quickly than with home-brew FPGA prototyping boards, he said.

“In the fully automated mode where you don’t make RTL changes, the [execution] speed is not so high,” Schirrmeister said, noting that the clock rate for most designs running on the prototyping platform will be in the 5MHz range. “Although the speed is limited, you get it fast.”

To increase the execution speed, the hardware team would then start to ‘black box’ parts of the design – typically those that impose the greatest bottleneck on clock rate. Recoded for the FPGA platform, those cores can be deployed in parts of the Protium S1 array of FPGAs or, in the case of standard interfaces, put onto expansion cards. The gradual optimization would let the target get into the hundreds of megahertz range in parallel with work on machines brought up on the automatically generated netlist.

The Protium S1 provides backdoor memory accesses, Schirrmeister said, allowing the rapid upload of new software images as well as the ability to tweak register contents. “You can run for a period of time, then stop the design and look at the registers and then force them to different values, maybe inject errors, and see whether it works from there.”

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