The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.
Cadence Design Systems
Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.
Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
But the bridge standard's European backers still need greater support from the big EDA vendors.
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
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