Cadence Design Systems

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.

The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.