Cadence Design Systems

May 3, 2016

Allegro release tackles new generations of PCB

The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.
May 3, 2016

Cadence boosts MAC count for neural networks

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.
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April 5, 2016

Cadence moves into safer design with Virtuoso changes

Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
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March 16, 2016

MEMS contest launches at DATE

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
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February 2, 2016

Cadence boosts compression with physical DFT tool

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
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December 18, 2015

Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
December 7, 2015

Cadence partners for photonic IC design

Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
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November 16, 2015

Cadence shifts emulation to the data center

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.
October 9, 2015

IMEC 5nm test chip to explore EUV and SAQP litho options

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
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