June 25, 2018
Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.
May 22, 2018
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 9, 2018
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
May 8, 2018
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
April 11, 2018
Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
April 10, 2018
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
February 28, 2018
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
September 12, 2017
ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
June 14, 2017
EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
May 30, 2017
Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.