Racyics puts FD-SOI design flow online

By Chris Edwards |  No Comments  |  Posted: May 11, 2017
Topics/Categories: Blog - EDA, IP  |  Tags: , , ,  | Organizations: , ,

Racyics has opened a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

The makeChip hosted design flow is backed by Cadence Design Systems and is aimed at the 22nm FD-SOI node. The online platform provides a full set of EDA tool installations together with process design kits (PDKs) and a selection of IP libraries. All tools and design data are linked by Racyics’ design flow and project-management system.

“We want to move start-ups, small and medium sized businesses, and academia to the leading-edge of the game. With makeChip, we enable them to quickly execute analog, mixed-signal and digital designs in [GlobalFoundries’] 22FDX technology, so they can develop the hardware basis for high-volume applications in the fields of IoT and Industry 4.0,” said Holger Eisenreich, CEO of Racyics.

“Our 22FDX technology is quickly becoming a platform of choice for market-focused applications that require low power and operational efficiency with an affordability advantage,” claimed Alain Mutricy, senior vice president of product management at GlobalFoundries. “This collaboration with Racyics and Cadence will help lower the barrier of entry for SMEs, start-ups, and academia.”

As part of the offering, Racyics provides its in-house 0.4V IP for 22FDX, and will be free of charge for non-commercial projects. The library is intended for very low-power designs. The company said two pilot projects are currently running on makeChip.

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