Cadence Design Systems

Machine learning is gradually moving into implementation and verification tools for EDA.

Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.

Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.