Fast process access gets Moortec onto 7nm

By Chris Edwards |  No Comments  |  Posted: February 1, 2019
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations: ,

Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits on SoCs that are increasingly vulnerable to the characteristics of those processes.

Originally founded as a design-service company in 2005, Moortec has carved out a niche as a supplier of on-chip instrumentation IP for measuring temperature, IR drop and process variations.

Ramsay Allen, vice president of marketing at Moortec, says: “It was in 2010 we started to design temperature sensors, then targeting the 65nm and 40nm nodes, mainly as design-services offerings. We realized there was a niche in the market not just for temperature but for others: process and voltage monitors. Since then, we’ve moved away from design services to become an IP vendor and focus on monitoring. We believe we are the only vendor focused on that.”

Now on the sixth generation of temperature sensor, Allen says the company has worked with 60 customers worldwide on a variety of processes, with 7nm becoming the latest to be added to the portfolio. The company’s first test chip for 7nm taped out last summer.

Scaling challenges

Scaling down into the finFET nodes in addition to 28nm, Allen notes the company has picked up increasing business in automotive, data centers and artificial-intelligence accelerator projects.

“It’s come about due to the scaling down of devices. You have ICs with temperature hotspots on the die as well as issues with voltage and IR drop,” Allen says. The sensors are used for a variety of tasks, from health checks through to support for dynamic voltage and frequency scaling strategies.

Oliver King, Moortec CTO, says the design teams need to get earlier access to tools and process kits in order to deliver silicon-proven cores to customers working at the leading edge.

“We want to work with market leaders on the tools. When you are early in the node. We want to work with a vendor that aims to be there first,” King says, and it is not possible to wait for the official release even from the tools suppliers working on those advanced nodes. “Take 7nm as an example. Our engagement started very early. We need access to tools before they were even officially released.”

Since the company’s work with on-die monitors for the 28nm generation, Moortec has employed the mixed-signal layout and implementation tools from Cadence Design Systems. Much of the custom design is for the hard IP that goes into the on-die monitors. But the company also uses the Innovus digital implementation tools for the digital controller core that customers can use to manage a number of on-die sensors.

“Although we are doing analog design inside our circuits, we are delivering blocks that fit in an ASIC flow. So we also have to deliver Liberty timing flows,” King adds, which calls on other aspects of the implementation and verification tools.

For the custom-design blocks, Moortec’s engineering team has had to deal with the changes forced by the use of finFET devices and much more restricted layout and routing on those nodes.

“Layout leads our design rather than the schematic. The schematic description of a transistor is just nowhere near the real device you’ve got the parasitics to take into account,” King says.

“The days of full-custom analog are a little bit past now. We have a mix of constraint-driven layout and layout based on tiling cells,” King adds, calling on automation in Virtuoso such as modgens to create parameterized circuitry. “Very little is done as freeform. We can do polygon pushing but that’s likely to be in I/O cells.”

Constraint-driven design makes it possible to deal with the complexity of the design rules and to turn around designs in a reasonable timeframe. “The area is not as compact as it theoretically could be but but the tradeoff comes in huge time savings,” King says.

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