Node-variant FinFET tweaks try to improve cost, performance
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of their finFET processes for the interim nodes they have extracted from existing 14nm and 10nm offerings. They used VLSI Technology Symposium to describe what they had done.
While the company works on bringing its EUV-based 7nm process to production readiness, Samsung Electronics has introduced what it calls an 8nm node, taking the step of using four levels of LE-based multiple patterning on the critical metal layers. Qualcomm worked with Samsung on the 8nm process. The communications specialist’s Jun Wan said LE^4 was used to support more complex routing than would be possible with the equivalent self-aligned multiple-patterning approach.
Hwasung Rhee of Samsung said: “Samsung strongly believes EUV is the right choice for 7nm. We also observed there is an empty space between 10nm and 7nm.”
The main change for 10nm is a reduction in the metal spacing at the lowest levels from 48nm to 44nm. Rhee said IP developed for the 10nm node would be usable on the variant process.
Wan said a CPU design on the 8nm process demonstrated a performance improvement of 40 per cent and 15 per cent less area.
At VLSI Technology Symposium, Samsung Electronics also disclosed that it had opted for a 6.75-track cell to push area down by around 15 per cent on its 11nm process compared to its predecessor, and claimed the design rules remain the same as the original 14nm node except for a tighter-space M2 layer. A 9-track cell option aims at performance instead, with frequency moving up by 9 per cent.
The fractional nature of the smaller cell library splits the library into two complementary transistors that, typically, will be used as matched two-fin devices. However there is also the option to boost one to three fins to increase the drive strength on, typically, a p-channel device.
GlobalFoundries has opted for the moniker 12nm for its derivative of the 14nm LPP process. Representing the foundry in the CMOS platforms session at the symposium, Hsien-Ching Lo said a test ring oscillator demonstrated a performance improvement of 15 per cent over the previous process. For its reduced track height option, GlobalFoundries has chosen a 7.5-track architecture, with designs expected to consume 16 per cent less power. Lo said the process team focused on reducing transistor resistance through better mobility, a higher doping level and changes to the epitaxy. Reducing the surface roughness of the fins helped improve mobility.