June 8, 2015
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
October 23, 2013
Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
March 19, 2013
The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.
November 16, 2012
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
October 16, 2012
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 9, 2012
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
