Cadence adds AI to PCB design
Cadence Design Systems has expanded its use of machine learning for EDA into PCB design, joining a growing number of suppliers who have decided it is a sector that needs the AI treatment.
Blog Topics
Curvilinear layout looks to wider adoption with mask speedups
Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
SEMI predicts strong 300mm growth to 2026
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Siemens harnesses machine learning for more comprehensive verification
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
DVCon Europe best paper speeds up memory-controller tests
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
A*Star lays out SiP applications choices at IEDM
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Imec adds MOL layer to potentially cut cell size 20%
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
PLATINUM SPONSORS
View All Sponsors