UVM Connect

April 17, 2023

Achieving functional coverage of multi-language designs

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

Article | Topics: Blog - EDA, - Verification | Tags: abstraction, functional coverage, systemc, SystemVerilog, TLM, transaction level modeling, UVM, UVM Connect | Organizations: DVCon, Siemens EDA