Achieving functional coverage of multi-language designs
There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
TLM
DVCon Europe takes in machine learning and stimulus for verification
Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
Three Accellera proposals aim for better TLM
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
DAC 2012: Synopsys marries virtual and FPGA prototyping
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
New SystemC reference simulator open for public comment
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.
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