TLM


October 17, 2018

DVCon Europe takes in machine learning and stimulus for verification

Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
Article  |  Topics: Blog - EDA  |  Tags: , , ,
November 12, 2015

DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols

High powered alliance develops TLM standards to address growing automotive and IoT concerns.
July 30, 2013

Three Accellera proposals aim for better TLM

Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
June 7, 2012

DAC 2012: Synopsys marries virtual and FPGA prototyping

Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
Article  |  Topics: Blog Topics, Commentary, ESL/SystemC, Verification  |  Tags: , , ,   |  Organizations:
February 9, 2012

New SystemC reference simulator open for public comment

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.
Article  |  Topics: Commentary, Blog - EDA, - ESL/SystemC, Industry Blogs, Standards  |  Tags: ,

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