Cadence adds AI to PCB design
Cadence Design Systems has expanded its use of machine learning for EDA into PCB design, joining a growing number of suppliers who have decided it is a sector that needs the AI treatment.
A number of suppliers are preparing their own AI-enabled releases, including longstanding PCB-tools providers and startups such as Celus, DeepPCB, and Quilter. Siemens EDA published a white paper on proposals for machine learning in PCB and system design late last year and Zuken will talk about its work on AI-assisted routing in a seminar series in the late spring.
Allegro X AI adds several automation features to the company’s PCB layout product, all of which need to run on Cadence’s cloud, which is hosted by AWS. Saugat Sen, vice president of R&D at the company said pricing for the AI-based services and whether the service would be charged per use or in the form of a subscription was yet to be determined. The service is still in a pre-release form, offered to a small group of lead customers, including Kioxia and Schneider Electric.
In its initial form, Allegro X AI focuses on placement, the routing of critical paths and the arrangement of metal and ground planes within the PCB. Sen claimed the company is working towards implementing full place-and-route for a future release. As the export from the AI mode is a regular Allegro file, the designer can use standard rip-up and replace procedures should the automated choices turn out to cause problems later on. However, he stressed that the AI mode performs signal- and power-integrity checks as part of the process to try to ensure the proposed layout will work correctly and also takes factors such as predicted congestion into account.
Complexity challenge
According to Cadence, the use of AI to place and partially route PCBs can cut days of design time out of the process in an environment where the task is getting more difficult.
“We believe PCB design is getting more complex because ICs are now coming with much larger pinouts. Even for simple to medium-sized PCBs, it can take on the order of two weeks to do manual placement. Doing this in hours is a transformative change,” Sen argued.
Sen claimed the reduction in time will allow more what-if analyses. One result of this may be that electrical engineers can do more analysis upfront to see how their decisions at the schematic level will affect performance and cost in the placed design without having to call on the PCB designers.
As has been the case with IC place-and-route aided by machine learning, the tool can come up with unexpected placement options that are more efficient. “The PCB designer can gain insights from the tool that they didn’t think of before. It can become a creative partner to assist in the design,” Sen claimed.
Sen said the AI does not rely on customer data for training or fine-tuning: the software has been trained on representative designs prepared by Cadence and synthetic variants. To make the best use of the tool, designers will need to apply constraints up-front as the automated layout is not an interactive process. “It is more akin to digital IC design where you have to be upfront in articulating constraints. But somebody who has used Allegro X is already familiar with our approach to constraints,” he said, which remains primarily a graphical environment rather than relying on the kinds of textual scripting used in chip design.
