UK projects builds models for quantum computer controls
Partners in the UK’s CryoCMOS Consortium have developed models that are expected to help deliver CMOS chips that can operate at the temperatures needed to work close to the delicate, heavily cooled circuitry inside quantum computers.
Memory specialist SureCore and lead partner in the consortium aims to use the PDK-quality transistors to design circuits able to handle 4K and 77K operation. Building sophisticated electronic controls that can work way below the normal CMOS range is key to reducing the amount of bulky cabling needed to connect the sophisticated controls to the core qubits. The long-distance connections needed today make it harder to scale up capacity and introduce delays that make dynamic error correction harder to implement.
To be able to develop the models, the consortium engaged Belgium-based Incize to conduct delicate measurements of CMOS test circuits in a cryogenic chamber.
“We picked Incize as it is one of the few commercial companies that specialises in precise cryogenic transistor measurements in the challenging conditions of a cryostat. You can’t just rearrange the probes on chip at will in a 4K cryostat. We are really pleased with the quality of the measurement data we received from Incize,” said SureCore CEO Paul Wells.
The measurement data was used by SemiWise to develop the novel transistor models, which handle operation at multiple process corners. A combination of measurement and simulation data is being used by SemiWise to re-center the foundry transistor SPICE models for cryogenic temperatures so that the 22FDX-node processes offered by GlobalFoundries can be used for reliable cryogenic circuit design.
The patented SemiWise re-centering technology allows the development of typical and corner transistor models as well as statistical mismatch models, all critical to the SRAM design process. SureCore aims to develop a suite of power-optimised, foundation IP including standard cells, SRAM, ROM and register files. Low power will be crucial to avoid the risk of CMOS transistors introducing too much heat into the cryostat.
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