March 30, 2023
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
February 28, 2023
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
January 31, 2023
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
January 18, 2023
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
January 6, 2023
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
January 4, 2023
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
December 12, 2022
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
December 9, 2022
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
December 5, 2022
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
December 1, 2022
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.