Blog Topics

Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.

Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.

Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.

The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.

New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.

Real Intent has developed a tool to check design and the potential for circuits to glitch.

Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.