July 14, 2023
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
July 12, 2023
Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
July 11, 2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
July 10, 2023
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
July 10, 2023
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
July 7, 2023
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
July 4, 2023
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
June 22, 2023
The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.
June 14, 2023
Siemens is integrating the Supplyframe platform with the Xpedition PCB-design software to give engineers better visibility into component availability.
June 12, 2023
AT&S and Imec partnered to develop a way of putting low-loss waveguides into conventional PCBs to support D-band automotive radar and 6G modules.