Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium. Engineers from Imec, Intel, and Samsung Electronics all found advantages to burying the power supply under the silicon substrate though there are major tradeoffs involved in how the connections get made to the transistors.
In work using two Arm cores on a test chip, Samsung Electronics reductions in area of 10 and 19 per cent along with a frequency improvement of 3.6 per cent. The delivery of power and ground rails in the Samsung design was through dedicated power-tap cells that lie between conventional standard cells. This frees up space above the cells that would otherwise by recognized as an obstruction by place-and-route tools. A further optimization made by the team was the use of variant cells to restrict how much they use upper metal layers – trading area against height, in effect – to improve the routability of congested areas. That led to an overall 2.4 per cent reduction in overall block area.
A pair of papers from Intel described how teams at the chipmaker applied backside power delivery to the existing Intel 4 process as a pathfinder for the forthcoming 20A and 18A nodes that are expected to put the technology the company has called PowerVia into production. This will be the successor to the buried power rail technology the company has embraced as an interim to backside delivery. With this approach, power is still supplied from the front but diverted into buried rails to reduce congestion in the middle metal layers.
Front to back
PowerVia removes the need to bring any power from the front side, using wafer bonding to attach the copper interconnect used to carry power and ground to the main silicon die, which itself is thinned to the point where there is very little substrate under the transistor. Rectangular vias at the top boundary of each standard cell carry power into the source contacts of transistors that need direct power-rail connections extended contact strips. The result of the change is a reduction in track height from 240nm to 210nm for the standard cell and the opportunity to relax M0 pitch from 30 to 36nm.
The Intel design-evaluation team created a test chip based around a four-processor, efficiency-core IP block that takes up around 22 million gates. Each module was implemented with power distribution around the standard cells in a slightly different way to let the team gauge how those choices affected IR drop and other metrics. The overall results, however, were good.
“Very early on in designs we found PowerVia designs produced much better routing quality. Signal wire length reduced by 20 per cent and total signal via count reduced 5 per cent,” said Manju Shamanna, senior hardware engineer at Intel. He added that this led to fewer buffers and inverters being added by the implementation tools, which in turn delivered lower overall leakage and an increase in usable clock frequency.
Another metric used by Intel was the amount of signal routing that could be completed at metal layer four and below. In the existing Intel 4 process, this figure was 73 per cent. But with backside power delivery, the proportion increased to 80 per cent.
There are ramifications for placement tools that designers will need to take into. Shamanna pointed out that the improved routing makes it possible to pack standard cells more tightly which could make it harder to perform late engineering change orders (ECOs). Longer traces also lose the side-benefit of shielding from power and ground lines in conventional frontside architectures. One answer to this used by the Intel team is to use a dedicated standard cell to bring a power or ground line to the frontside that can be used as a shield for sensitive connections.
To demonstrate the improvements in voltage stability compared to frontside power delivery, the designers peppered the cores with on-die IP-drop detectors. In the cores tested, Intel found IR drop fell by around 30 per cent. “We expect to see an IR-drop delta of more than 40 per cent on products,” Shamanna said, based on insights revealed by analysis of the difference in power-network efficiency among the different cores.
Analysis of the effects of extreme wafer thinning on the core transistors by another team at Intel showed that any changes are negligible. They also found little change thermo-mechanical behavior overall and “robust” electromigration performance. “In short, all reliability considerations are healthy,” claimed Walid Hafez, technology-development engineer at Intel.
Three main options
The approach chosen by Intel represents one of three major power-delivery schemes identified by research institute Imec, which developed many of the early ideas in this area and which continues to investigate its ramifications for manufacturing and design. The main options are the buried power rail, via-middle schemes similar to PowerVia where the power contact is made above the silicon surface, and a direct backside contact scheme. The last will be the toughest to achieve because it requires high overlay precision when the wafers are bonded. Imec researcher Sheng Yang pointed out there is a high risk of shorts with the backside contact scheme though it has the benefit of offering high layout density. At the A14 node it may be the only realistic choice as the expected scaling in cell track height will likely leave insufficient space for the through-silicon via (TSV) once the need for cell-cell isolation is taken into account. Resistance may also be an issue though a change to via metals may overcome this issue. The via-middle approach may win out in high-performance computing in the meantime where maximum density is not essential.
Imec senior fellow Eric Beyne described how the research institute has worked on an adaptive lithography scheme to improve the alignment between the power wafer and the main silicon wafer, which will often be distorted laterally by the various processing steps it has been through by the time it is thinned ready for attachment to the power carrier. There will be significant variations in overlay across the surface even if the overall wafers are aligned perfectly. The proposed solution is to adapt the lithography used on the power interconnect and contacts to the silicon wafer in the stepper itself.
Beyne added that the use of backside power delivery could make it easier to build logic and memory stacks, with TSVs into the upper memory device providing power to those, less energy-hungry arrays. The memory and logic wafers would be bonded face-to-face and the logic wafer bonded to the power delivery network carrier.