October 31, 2023
Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
October 31, 2023
Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
October 25, 2023
This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
October 25, 2023
The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
October 24, 2023
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
October 16, 2023
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
October 9, 2023
From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
October 9, 2023
Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.
October 6, 2023
MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
October 5, 2023
Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.