Ferroelectric memory moves closer with VLSI experiments

By Chris Edwards |  No Comments  |  Posted: July 20, 2023
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A variety of papers presented at this year’s VLSI Symposium have underlined the sensitivity of the new generation of ferroelectric devices to the way the delicate thin films needed to implement them are formed and used. But the work brings the possibility of a high-density, low-power non-volatile memory closer.

Though ferroelectric memories have been in production since the 1980s, manufacturers have found it difficult to scale density beyond the kilobyte range largely because of difficulty integrating the materials needed for the memory cells and their electrodes and CMOS processes. The discovery in the late-2000s by Qimonda of ferroelectric behavior in the leading high-k dielectric developed for DRAMs and CMOS transistors changed the prospects for ferroelectric circuitry not least because it was found to be one of the few metal oxides that is thermodynamically stable on silicon along with the close relative hafnium zirconium oxide (HZO).

In contrast to traditional PZT-based FRAMs, which employ a silicon transistor paired with a ferroelectric capacitor, the work on hafnium-based versions has opened up the possibility of creating a memory cell on the gate of a CMOS transistor to form a FeFET as well as in tunnel junctions analogous to those used in magnetic memories. This has opened up the possibility of building 3D crossbar memories as well as NAND-type arrays.

Production conditions

Work has progressed only gradually because ferroelectricity in the dielectric is driven heavily by the conditions used to deposit and anneal it. Only one phase of the three into which it crystallises delivers the asymmetry needed for ferroelectricity. Successive experiments have shown this orthorhombic phase forms most naturally under a capping layer of a metal such as tungsten.

The papers at VLSI the year have shown how temperature, stress and even styles of operation are likely to play a role in the development of commercially viable memories. One feature of hafnium oxide explored at VLSI this year is that scaling yields enhanced properties in a way that is not seen in PZT, which needs film thicknesses on the order of 100nm but which does deliver far higher retention and endurance figures.

Zucheng Cai of the University of Tokyo described the work on scaling down the thickness of hafnium-based dielectrics to as little as 4.6nm. Earlier work pointed to a reduction in programming and erase voltages with thinner films, which should help with lifetime. But Cai pointed out the work carried out by the team was the first systematic study to understand the effects of scaling in FeFETs. In the experiments, the thinner films showed higher consistency, a lower subthreshold swing for transistor switching and a doubling in endurance compared to the thickest films, though still only 100,000 cycles.

One issue with the hafnium films is that the memory window tends to narrow over time, caused by a combination interface degradation, worsened by high programming voltages, and ferroelectric fatigue. However, several papers have identified that the fatigue is reversible by applying moderate frequency pulses. These pulses seem to be able to redistribute oxygen vacancies that play a role in enhancing the ferroelectric effect. The Tokyo experiments showed that though interface degradation is permanent, thin films react better to the recovery pulses.

Work at KAIST underlined the likely importance of crystal orientation in maximizing the memory window and how different structures will affect those choices. Song-Hyeon Kuk, PhD student at the Korean institute explained that surface treatments can be used to control the crystal orientation of epitaxially grown hafnium zirconium oxide. “In a FeFET, surface orientation affects not just carrier mobility but polarizability,” he said, adding that the orientation also has an effect on thermal budget. The necessary ferroelectric phases forms at a lower temperature on a silicon surface with a Miller index of (100) though the (110) silicon surface demonstrates higher overall polarizability. However, the oxides formed on a (100) surface achieved a larger memory window, making this orientation the most favorable for planar FeFETs. In contrast, other orientations may work better for the vertical channels needed for 3D NAND-type memory arrays.

Interface concerns

The interfaces between the gate electrode and channel also play key roles in determining performance it seems. In reporting work by National Taiwan University (NTU), Yu-Rui Chen pointed out interface layers tend to reduce the memory window in FeFETs. Others pointed that endurance also suffers because traps form readily in these layers.

In making a double nanosheet FeFET, the NTU team avoided creating an interface layer between the primarily germanium channel and a superlattice sandwich of hafnium and hafnium-zirconium oxides. The resulting structure showed endurance as high as 1011 operations with retention demonstrated to 100,000 seconds though the team believes this can be extrapolated to 10 years.

Interfaces can form readily because of oxidation between processes so a team from the National University of Singapore worked on an in-situ deposition scheme for a FeFET structure aimed at BEOL integration where the HZO was sandwiched between two metallic titanium nitride layers, all under vacuum. To improve the area efficiency and cell capacity, the team developed a finned structure.

Operating temperature also plays a key role in performance, according to work reported by researchers from the Georgia Institute of Technology. Sharadindu Gopal Kirtania explained how lack of endurance could be a major hurdle to bringing in FeRAM as a last-level cache in high-performance servers. The non-volatility would greatly help with power consumption in these large caches and 3D structures would massively improve density over SRAM. Room temperature endurance at around one million writes on the devices they have been working on rules out their use. However, they found that operating under cryogenic conditions, at around 77K, performance improves not just on endurance but write speed and voltage. According to their experiments, endurance may be practically unlimited. The reason seems to be that the creation of oxygen vacancies that lead to wearout seems to be predominantly thermally activated. Cryogenic operation greatly reduces their formation, extending the usable lifetime far further.

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