EDA

Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions about the nascent market.

EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.

Manufacturing giant says we need a new category of WPUs - wearables processing units - to create a mass market and that ARM needs to go smaller than the MO.

ARM and Cadence have teamed up to show how system-level and implementation-level representations of a mixed-signal design can be linked together and kept in sync as the project progresses.

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.

Two of the custom designs presented at the 26th Hot Chips in Cupertino exemplified the problems caused by increasing power density and the benefits of looking at heat removal at the system level.

High peak-to-average ratios inherent in 4G/5G modulation schemes are driving the circuitry controlling RF PAs to become more modeling-oriented.

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.