Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
EDA
Post-silicon devices: maybe it’s in the way they move
A research-focused session at DAC 2014 looks at using coupled oscillators rather than charge transfer to process data.
Emulation ‘heart of ESL’
The emulator has become the cornerstone of embedded system level (ESL) design on SoC projects, analyst Gary Smith claimed in a speech ahead of DAC 51.
Synopsys adds vector DSP operations to ARC EM processor IP
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
Do not trust the cores, Trojans
If someone put a piece of RTL into your SoC designed to leak information to the outside world, or simply kill the device stone dead, could you spot it?
IP takes center stage in push towards systems engineering
At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
On-chip interconnect startup uses network theory to sidestep deadlocks
NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Pulsic opts for “layout early, layout often” strategy
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Vorsprung durch 3D technik for Audi
The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
Multicore fastSpice extends reach
Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.
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