EDA

Two of the custom designs presented at the 26th Hot Chips in Cupertino exemplified the problems caused by increasing power density and the benefits of looking at heat removal at the system level.

High peak-to-average ratios inherent in 4G/5G modulation schemes are driving the circuitry controlling RF PAs to become more modeling-oriented.

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.

Chinese foundry Semiconductor Manufacturing International Corporation (SMIC) is to get a helping hand to develop a production-class 28nm process from Qualcomm Technologies.