New flows needed for the ‘insects of the SoC world’

By Chris Edwards |  No Comments  |  Posted: September 17, 2014
Topics/Categories: Blog - EDA, Embedded, IP  |  Tags: , , , , ,  | Organizations:

Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions he has made about a movement that he said has clearly become the buzz-phrase of 2014 and one that’s becoming increasingly useless.

“IoT is such a broad phrase but it’s not very useful. It’s uselessness as a phrase will become more apparent as we go forward,” Rowen claimed, as volume silicon begins to appear that aims at specific markets, such as the smart home, industrial, automotive, medical and wearable.

The one thing they have in common is need for specialization and low energy consumption, Rowen said: “But they will vary in applications and their interaction with the cloud. The IoT label doesn’t do justice to the diversity of devices being designed. At the lowest extreme you have very low data rate sensing nodes. Then you move to higher sampling rates but not doing much locally or you may have smart nodes doing exhaustive analysis.”

A smart-home device such as a voice-recognizing thermostat, for example, may fall back on communications to the cloud regularly to do the heavy lifting of speech processing. But a driver-assistance system for a car cannot afford to do that and will need to do most of its own processing.

Farewell IoT

“What we are going to see is that the IoT label will be replaced by much more specific language,” Rowen said. But similarities in architecture will drive different approaches to SoC design than those that are prevalent in what is today regarded as mainstream SoC design. “They will use just-enough digital, be rich in analog and feature energy-obsessive design.”

The key to energy efficiency lies in the system architecture that, in turn, makes the interaction between specific software, digital, and analog subsystems much more crucial, according to Rowen. “There really is a bifurcation that we see in the design of SoCs. There is a gap opening up between the types of design done for general-purpose all-in-one systems, those designed for cellphones, PCs, servers gateways, and the IoT SoCs that are highly specialized, low energy devices.

“The general-purpose devices are the mammals of the SoC world. They are quite adaptive but there are relatively few varieties. They are extreme-scale SoCs: they continue to push the limit on Moore’s law. But the specialized IoT-oriented SoCs are extreme-fit SoCs. It’s all about being at the right cost and power points. They are like the insects of the animal world: they are highly specialized to the ecological niche that they find themselves in,” said Rowen, pointing out the three orders-of-magnitude difference in the number of mammalian and insect species. “These more specialized device will often be built at 28nm and above, not on 16nm finFET and below. It is much more about rapid adaptation to emerging or special function apps.

Change in focus

“We will stop worrying about the death of Moore’s Law. It is certainly the case that the physics of building those fine-geometry devices is getting harder and harder. The number of players at the bleeding edge will continue to go down slowly. We have ample historical proof that people can find creative ways to push the edge of smaller geometries. But more important is that much of the SoC design world won’t give a damn because in the nodes we already have available the capacity for digital and analog [for IoT-class devices].

“There is so much benefit in specialization that we won’t need to build huge devices. The shift will really go away from pushing the envelope of transistor count to pushing the envelope on architectural creativity. I think design starts are going to respond to this explosive opportunity for these insect species.

“The bifurcation will extend into distinct IP and tool flows,” Rowen added. He pointed to one experiment at Cadence where using Spice to characterize the design rather than a traditional standard-cell flow helped cut the voltage on a test design to around 0.5V, reducing power per megahertz to around 1µW for the Tensilica-architecture processor. The focus on specialization for energy will also drive what he called “cognitive layering” where tasks are divided according to their frequency of operation into nearly always-on and rarely-on categories, with the rarely-on category able to make higher demands on power.

“The cognitive-layering principle will drive the competition between always-on and rarely-on subsystems. A process technology such as 40nm can easily accommodate that range of processors without costing too much in silicon and provide the illusion of being always on. It will be the role of the systems architect to turn the illusion into the reality of almost always off. We will see that software and processor will be closely coupled to each other,” Rowen claimed.

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