ARM unveils superscalar addition to Cortex-M microcontrollers

By Chris Edwards |  No Comments  |  Posted: September 24, 2014
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , ,  | Organizations: , ,

Freescale and STMicroelectronics have committed to use a high-end version of the Cortex-M processor architecture that borrows elements from ARM’s Cortex-R family for safety-critical applications as well as adding the option of cache memory.

ARM’s M7 uses a six-stage superscalar pipeline to provide higher performance than the current top-end processor from the microcontroller family, the M4. Instructions are issued in order but allowed to complete out of order, a standard approach to dual-issue superscalar designs as it provides reasonable performance with low silicon cost. Out-of-order completion prevents long-latency operations such as writes to memory from stalling the pipeline if there are no data dependencies.

As most execution units are duplicated, the company said the M7 is designed to be able to issue most combinations of instructions, so that it is not restricted to issuing integer and floating-point instructions in parallel. According to ARM, when implemented on a 40nm process, the M7 can hit 400MHz and reach an EEMBC Coremark score of 2000 or 5 Coremarks per MHz. Typically, that order of Coremark/MHz score is seen on dual-core engines although results published by Imagination Technologies for an FPGA-based proAptiv – an out-of-order design aimed at media computing – show it as roughly in the same range on the benchmark.

ST has chosen to use a 90nm process with onchip flash for its F7 microcontrollers initially, targeting a frequency of 200MHz. ST said it is using both cache and a memory accelerator developed by the chipmaker to support no-wait-state operation with the dual-pipeline processor core. ST said it is sampling devices now to lead customers.

The M7 core includes the DSP and floating-point support introduced with the M4, adding a few extra floating-point instructions. ARM said code written for the M4 will run unchanged on an M7.

The M7 incorporates several safety-related features from the current R series, including support for memory ECC and the ability to run two cores in lock-step. Full data trace is available for debugging and the company has committed to delivering documentation to support certification to standards such as ISO 26262. Although the M7 does not make significant changes to its memory-protection support compared to the other in the M series, the new core can support 16 discrete regions of protected memory rather than eight.

There are number of memory options as well as support for AXI interconnect with 64bit data transfers. As well as tightly coupled memories, already supported by the lower-end M series, the M7 can work with caches to help support larger systems with significant amounts of off-chip memory.

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