Simulations point to better performance for Intel 14nm finFET

By Chris Edwards |  No Comments  |  Posted: August 19, 2014
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations: ,

In the wake of Intel’s release of images and a few details on its 14nm finFET process, Gold Standard Simulations founder and CEO Professor Asen Asenov has run simulations to work out how much of an improvement the rectangular shape is over the 22nm process’s original tapered shape.

When Intel published details on the 22nm process, Asenov pointed out a number of issues that the shape would have on performance. In his latest blog page, he notes that Intel has managed to achieve a ‘better’ rectangular shape, at least above the shallow trench isolation (STI) boundary – the tapered shape makes it easier to fill the gaps between fins with oxide.

“From a first glance the reduced fin pitch and increased fin height suggests more than 1.7x improvement of the drive current,” Asenov writes. “However, the drive current will be strongly affected by the contact resistance and the extrinsic access resistance, both of which are expected to increase with the scaling of the pitch.”

However, Asenov says the simulations do not take into account contact and similar resistances, which will tend to reduce overall performance.

As Intel has taken the trouble to make the fin more rectangular despite the manufacturing challenges in doing so suggests that the company has seen a significant-enough performance increase to justify it.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors