EDA

The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.

Does the internet of things (IoT) require a change in design techniques? A number of people involved in the EDA industry reckon it does.

ARM's latest core, the dual-issue M7 borrows features from the Cortex-R family for safety-critical applications as well as adding the option of cache memory.

Cisco has decided to buy memory-controller specialist Memoir Systems and absorb the technology into its Insieme business unit, which specializes in data-center switch technologies, a move that underlines the issues facing small IP suppliers and their customers.

Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions about the nascent market.

EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.

Manufacturing giant says we need a new category of WPUs - wearables processing units - to create a mass market and that ARM needs to go smaller than the MO.

ARM and Cadence have teamed up to show how system-level and implementation-level representations of a mixed-signal design can be linked together and kept in sync as the project progresses.

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.