Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Archives
From iterative to in-design DRC and debug for place and route
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Samsung moves further into 3D for denser flash
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec cuts transistor gap to less than 20nm with forksheets
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
IEDM looks for papers across 2D devices to 3DICs
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Would you prefer a hypervisor or a multicore framework?
Determining which embedded technique to adopt is more than just a question of what cores the system has.
PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.