Pulsic goes freemium with analog-preview tool
Pulsic has adopted the freemium approach with a tool that gives designers of analog circuits previews of how they will be implemented on-chip.
Archives
How to simplify ESD verification with pre-coded checks
Electrostatic discharge verification is becoming increasingly hard to achieve but automated pre-loaded checks can now help.
How to use virtual mode in emulation
Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.
Design house recommends earlier start to flip-chip bump layout
Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.
A new methodology addresses the increasing challenge of reset domain crossing
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Plasmonics may point way to faster interchip comms
Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Arm expands cloud migration on Arm-based machines at AWS
Arm is pushing more work onto Arm servers in the AWS cloud as it encourages EDA vendors to port their tools to the architecture.
Macronix proposes 3D to breathe life back into NOR flash
At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.
Mentor rebrands as Siemens EDA
Mentor, a Siemens business, has rebranded as Siemens EDA, almost almost four years after the EDA company was acquired.