July 27, 2020
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
January 29, 2020
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
October 29, 2019
Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
October 7, 2019
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
May 23, 2019
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
February 19, 2019
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
November 7, 2018
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
May 1, 2018
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
February 12, 2018
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
March 2, 2017
Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.