simulation

March 4, 2014

Synopsys targets 5X performance gain with integrated verification suite

New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
May 7, 2013

CDNLive EMEA: Cadence brings IEEE 1801 into simulation update

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Topics: Blog Topics, Design to Silicon, Verification  |  Tags: , , , , ,   |  Organizations:
March 19, 2013

SoC prototyping ascends the learning curve

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.
October 8, 2012

Synopsys buys EVE and the death of dogma

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.

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