simulation

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.

Stability is the watchword as AMS and MEMS specialist Tanner retains much of its independence - a 'start-up with a billion-dollar company behind us'.

The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs

National Instruments has developed a kernel for Spice analog simulations that can be downloaded for faster performance on the FPGAs inside CompactRIO hardware.

Verify early and simulate as little as possible - the idea is familiar but how do you get there?

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.