simulation

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs

National Instruments has developed a kernel for Spice analog simulations that can be downloaded for faster performance on the FPGAs inside CompactRIO hardware.

Verify early and simulate as little as possible - the idea is familiar but how do you get there?

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.

New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.