Imperas Software has released a free instruction set simulator that covers the OpenHW Group’s implementations of the RISC-V processor architecture.
The Imperas riscvOVPsimCOREV can be configured to behave like any of the cores in the OpenHW CORE-V processor IP portfolio, including the RTL-frozen CV32E40P (formally known as PULP RI5CY) as well as the CV32E40S and CV32E40X cores. Also supported is the forthcoming CVA6-32/64bit core (formally known as PULP Ariane) and Imperas plans to cover other processors in the CORE-V roadmap.
“Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores,” said Jérôme Quévremont, Thales Research & Technology and vice-chair of OpenHW Cores Task Group. “The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.”
Implemented as closed-source freeware, the riscvOVPsimCOREV RISC-V model covers commercial as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license, and is available for download.