SVA

January 29, 2020

Toward more efficient formal strategies for deadlock

Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.

Article | Topics: Blog Topics, Verification | Tags: assertions, deadlock, formal verification, property checking, simulation, SVA, SystemVerilog | Organizations: Siemens EDA

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