DVCon USA 2019 preview: SmartDV

By TDF Staff |  No Comments  |  Posted: February 19, 2019
Topics/Categories: Conferences, Verification  |  Tags: , , ,  | Organizations: ,

SmartDV will demonstrate the two latest additions to its verification IP portfolio at DVCon USA (Doubletree Hotel, San Jose, February 25-28): TileLink verification IP for RISC-V-based systems and the SimXL synthesizable transactors for accelerating system-level SoC testing on hardware emulators and FPGA prototyping platforms. The company will be exhibiting at Booth #801.

SmartDV Tile Link verification IP

TileLink verification IP verifies the TileLink chip-scale interconnect fabric standard. This is an open-source, high-performance and scalable cache-coherent fabric for RISC-V-based SoC designs. It aims to speed TileLink implementation and comprehensive verification and is compliant with standard TileLink specifications. The company says that it offers faster testbench development, more complete verification with built-in coverage analysis and simplified results analysis.

TileLink Verification IP runs on simulation environments such as Synopsys VCS, Cadence Design System’ Incisive Enterprise Simulator, and Mentor’s ModelSim and Questa.

Smart DV SimXL

SimXL is a configurable and reusable plug-and-play interface verification solution based on industry-standard hardware verification languages. It runs on Cadence’s Palladium, Mentor’s Veloce Strato, and Synopsys’ ZeBu emulation platforms, as well as any custom FPGA prototyping tool.

It is compliant with most popular standards’ specifications, including those for automotive, serial bus, memory, MIPI, networking, SoC interconnect fabrics, storage and video protocols.

It has the same functionality and performance as SmartDV’s verification IP for simulation, featuring advanced commands, configurations and a status reporting interface for ease of use and debug. An interface based on UVM, OVM, SystemVerilog and SystemC controls SimXL.

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